Christian Panis Scalable DSP Core Architecture Addressing Compiler Requirements

This thesis considers the definition and design of an embedded configurable DSP (Digital Signal Processor) core architecture and will address the necessary requirements for developing an optimizing high-level language compiler. The introduction provides an overview of typical DSP core architectural features, briefly discusses the currently available DSP cores and summarizes the architectural aspects which have to be considered when developing an optimizing high-level language compiler. The introduction is followed by a total of 12 publications which outline the research work carried out while providing a detailed description of the main core features and the design space exploration methodology. Most of the research work focuses on architectural aspects of the configurable RISC (Reduced Instruction Set Computer) DSP core based on a modified Dual-Harvard load-store architecture. Due to increasing application code size and the associated configuration aspect the use of automatic code generation by a high-level language compiler is required. To generate code efficiently requires that the architectural aspects be considered as early as definition stage. This results in an orthogonal instruction set architecture with simple issue rules. Architectural features are introduced to reduce area consumption and power dissipation to fulfill requirements of SoC (System-on-Chip) and SiP (System-in-Package) applications and close the gap between dedicated hardware implementations and software based system solutions. Code density has a significant influence on the area of the DSP sub-system, thus xLIW (scalable Long Instruction Word) is introduced. An instruction buffer allows the reduction of power dissipation during execution of loop-centric DSP algorithms. Simple issue rules and exhaustive predicated execution feature enable efficient cycle and power execution of control code. The scalable DSP core architecture introduced herein allows parameterization of the main architectural features to application specific requirements. To make use of this feature it is necessary to analyze the requirements of the application. This thesis introduces a design space exploration methodology based on a C-compiler and a cycle-true instruction set simulator. A unique XML-based configuration file is used to reduce the implementation and validation effort for configuring the tool-chain, updating documentation and for automatic generation of parts of the VHDL-RTL core description.